Display panel and method of fabricating the same

ABSTRACT

A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower groove is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper groove is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper grooves. A luminescent device is disposed on the organic layer and overlaps the first region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a Continuation ofco-pending U.S. patent application Ser. No. 17/063,698, filed on Oct. 5,2020, which is a Continuation of U.S. patent application Ser. No.16/115,730, filed on Aug. 29, 2018, which claims priority under 35U.S.C. § 119 to Korean Patent Application No. 10-2017-0133551, filed onOct. 13, 2017; Korean Patent Application No. 10-2018-0017945, filed onFeb. 13, 2018; and Korean Patent Application No. 10-2018-0029301, filedon Mar. 13, 2018, the contents of which are hereby incorporated byreference in their entirety.

TECHNICAL FILED

The present disclosure relates to a display panel and, morespecifically, to a display panel and a method of fabricating the displaypanel.

DISCUSSION OF THE RELATED ART

A display device includes a plurality of pixels and a driving circuit(e.g., a scan driving circuit and a data driving circuit) forcontrolling the plurality of pixels. Each of the pixels includes adisplay element and a pixel driving circuit for controlling the displayelement. The pixel driving circuit includes a plurality of thin-filmtransistors that are organically connected to each other.

SUMMARY

A display panel includes a base layer having a first region and a secondregion that is bent with respect to the first region. At least oneinorganic layer overlaps both the first region and the second region andis disposed on the base layer. A lower groove is formed within the atleast one inorganic layer and overlaps the second region. A firstthin-film transistor is disposed on the at least one inorganic layer andincludes a silicon semiconductor pattern overlapping the first region. Asecond thin-film transistor is disposed on the at least one inorganiclayer and includes an oxide semiconductor pattern overlapping the firstregion. A plurality of insulating layers overlap both the first regionand the second region. An upper groove is formed within the plurality ofinsulating layers and the upper groove is extended from the lowergroove. A signal line electrically connects to the second thin-filmtransistor. An organic layer overlaps both the first region and thesecond region and is disposed in both the lower groove and the uppergroove. A luminescent device is disposed on the organic layer andoverlaps the first region.

A method of fabricating a display panel includes forming at least oneinorganic layer on a base layer. The base layer includes a first regionand a second region extended from the first region. The at least oneinorganic layer overlaps the first region and the second region of thebase layer. A silicon semiconductor pattern is formed on the at leastone inorganic layer. The silicon semiconductor pattern overlaps thefirst region of the base layer. A first control electrode is formed onthe silicon semiconductor pattern. The first control electrode overlapsthe silicon semiconductor pattern, with a first insulating layerinterposed between the first control electrode and the siliconsemiconductor pattern. An upper electrode is formed on the first controlelectrode. The upper electrode overlaps the first control electrode,with a second insulating layer interposed between the upper electrodeand the first control electrode. A third insulating layer is formedcovering the upper electrode. An oxide semiconductor pattern is formedon the third insulating layer. A second control electrode is formed onthe oxide semiconductor pattern, the second control electrode overlapsthe oxide semiconductor pattern. A fourth insulating layer is formedcovering the second control electrode. A first etching step is performedincluding partially removing the first to fourth insulating layers,thereby forming a first contact hole and a second contact holerespectively exposing a first portion and a second portion of thesilicon semiconductor pattern and forming an upper groove exposing aportion of the at least one inorganic layer overlapped with the secondregion. A second etching step is formed including partially removing thefourth insulating layer, thereby forming a third contact hole and afourth contact hole respectively exposing a first portion and a secondportion of the oxide semiconductor pattern, and of partially removingthe at least one inorganic layer, thereby forming a lower groove in thesecond region of the at least one inorganic layer, the lower grooveextending from the upper groove. An electrode forming step is performedincluding forming a first input electrode and a first output electrode,which are respectively connected to the first portion and the secondportion of the silicon semiconductor pattern, and forming a second inputelectrode and a second output electrode, which are respectivelyconnected to the first portion and the second portion of the oxidesemiconductor pattern. An organic layer is formed covering the firstinput electrode, the first output electrode, the second input electrode,and the second output electrode, the organic layer being disposed withinthe upper groove and the lower groove. A third etching step is performedincluding partially removing the organic layer, thereby forming a fifthcontact hole exposing the first output electrode. A luminescent deviceis formed, which is electrically connected to the first outputelectrode, on the organic layer.

A method of fabricating a display panel includes forming at least oneinorganic layer on a base layer. The base layer includes a first regionand a second region extended from the first region. The at least oneinorganic layer overlaps both the first region and the second region ofthe base layer. Insulating layers are formed overlapping both the firstregion and the second region of the base layer. Semiconductor patternsare formed, overlapping the first region of the base layer, on the atleast one inorganic layer, the semiconductor patterns including asilicon semiconductor pattern and an oxide semiconductor pattern. Afirst etching step is performed including partially removing theinsulating layers to expose a portion of the silicon semiconductorpattern and a portion of the at least one inorganic layer overlappingthe second region. A second etching step is performed includingpartially removing the insulating layers, thereby exposing a portion ofthe oxide semiconductor pattern and removing a portion of the at leastone inorganic layer overlapping the second region. Electrodes areformed, which are connected to the exposed portion of the siliconsemiconductor pattern and the exposed portion of the oxide semiconductorpattern. An organic layer is formed covering the electrodes, the organiclayer being disposed within the removed portion of the at least oneinorganic layer and the removed portion of the insulating layers. Aluminescent device and a signal line are formed on the organic layer.The luminescent device and the signal line are electrically connected tocorresponding ones of the electrodes. The second region is bent.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the present disclosure and many of theattendant aspects thereof will be readily obtained as the same becomesbetter understood by reference to the following detailed descriptionwhen considered in connection with the accompanying drawings, wherein:

FIGS. 1A and 1B are perspective views illustrating a display panelaccording to an exemplary embodiment of the inventive concept;

FIG. 2 is a plan view illustrating a display panel according to anexemplary embodiment of the inventive concept;

FIG. 3A is an equivalent circuit diagram illustrating a pixel accordingto an exemplary embodiment of the inventive concept;

FIGS. 3B and 3C are cross-sectional views illustrating a portion of apixel according to an exemplary embodiment of the inventive concept;

FIGS. 4A and 4B are cross-sectional views illustrating a bending regionof a display panel according to an exemplary embodiment of the inventiveconcept;

FIGS. 5A to 5M are cross-sectional views illustrating a process offabricating a display panel according to an exemplary embodiment of theinventive concept;

FIGS. 6 to 9 are cross-sectional views illustrating a portion of adisplay panel according to an exemplary embodiment of the inventiveconcept;

FIGS. 10A to 10G are cross-sectional views illustrating a portion of adisplay panel according to an exemplary embodiment of the inventiveconcept; and

FIGS. 11A to 11L are cross-sectional views illustrating a portion of adisplay panel according to an embodiment of the inventive concept.

DETAILED DESCRIPTION

Exemplary embodiments of the inventive concept will now be describedmore fully with reference to the accompanying drawings. The inventiveconcept may, however, be embodied in many different forms and should notbe construed as being limited to the embodiments set forth herein. Inthe drawings, the thicknesses of layers and regions may be exaggeratedfor clarity. Like reference numerals in the drawings and specificationmay denote like elements, and to the extent that a detailed descriptionof some elements are omitted, it may be assumed that these elements areat least similar to corresponding elements that are described elsewherein the specification.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent.

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

FIGS. 1A and 1B are perspective views illustrating a display panel DPaccording to an exemplary embodiment of the inventive concept. FIG. 2 isa plan view of the display panel DP according to an exemplary embodimentof the inventive concept. FIG. 2 illustrates connection structurebetween elements (e.g., pixels PX, a driving circuit GDC, and signallines SGL) constituting the display panel DP.

A plane of a front surface DP-FS of the display panel DP in an unfoldedstate may be parallel to a plane defined by a first direction axis DR1and a second direction axis DR2. A direction normal to the front surfaceDP-FS of the display panel DP (e.g., a thickness direction of thedisplay panel DP) will be referred to as a third direction axis DR3. Ineach of the various layers constituting the display panel DP, a top orfront surface may be differentiated from a bottom or rear surface, basedon the third direction axis DR3. Hereinafter, first to third directionsmay be directions indicated by the first to third direction axes DR1,DR2, and DR3, respectively, and will be identified with the samereference numbers.

As shown in FIG. 1A, the front surface DP-FS of the display panel DP mayinclude a display region DP-DA, which includes the pixels PX to be seenby a user, and a non-display region DP-NDA, which is disposed adjacentto the display region DP-DA. The non-display region DP-NDA may be aregion, in which the pixels PX are not disposed. Some of the signallines SGL and/or the driving circuit GDC may be disposed in thenon-display region DP-NDA.

As shown in FIG. 1A, the display region DP-DA may be rectangular ortetragonal. The non-display region DP-NDA may surround the displayregion DP-DA. However, the inventive concept is not limited thereto, andthe shapes of the display region DP-DA and the non-display region DP-NDAmay be otherwise arranged. For example, the non-display region DP-NDAmay be disposed in only two regions of the front surface DP-FS, whichare opposite to each other in the first direction DR1. In an exemplaryembodiment of the present inventive concept, the display region DP-DAmay be circular.

According to an exemplary embodiment of the present inventive concept, aportion of the non-display region DP-NDA may have a width (e.g., alength in the second direction DR2) that is smaller than that of thedisplay region DP-DA. This may make it possible to reduce an area of abending region, as will be described below.

As shown in FIG. 1B, the display panel DP may be bent, and as a resultof such a bending, the display panel DP may be divided into a first ornon-bending region NBA and a second or bending region BA. When thesecond region BA is in the bent state, the second region BA may includea curvature region CA, which is bent with a specific curvature, and afacing region FA, which faces the first region NBA.

As shown in FIG. 2 , the display panel DP may include a driving circuitGDC, a plurality of signal lines SGL, a plurality of signal pads DP-PD,and a plurality of pixels PX.

The pixels PX may be classified into a plurality of groups, according todisplay colors of the pixels. For example, the pixels PX may include redpixels, green pixels, and blue pixels. In an exemplary embodiment of thepresent inventive concept, the pixels PX may further include whitepixels. Even when pixels are included in different groups, the pixeldriving circuits of the pixels may be configured to have the samestructure.

The driving circuit GDC may include a scan driving circuit. The scandriving circuit may be configured to generate a plurality of scansignals and sequentially output the scan signals to a plurality of scanlines GL to be described below. In addition, the scan driving circuitmay be configured to output other control signals to a driving circuitof the pixel PX.

The scan driving circuit may include a plurality of thin-filmtransistors that are formed by the same process as the driving circuitof the pixel PX (e.g., by a low temperature polycrystalline silicon(LTPS) process or a low temperature polycrystalline oxide (LTPO)process).

The signal lines SGL may include scan lines GL, data lines DL, a powerline PL, and a control signal line CSL. Each of the scan lines GL may beconnected to a corresponding pixel of the plurality of pixels PX, andeach of the data lines DL may be connected to a corresponding pixel ofthe plurality of pixels PX. The power line PL may be connected to eachof the pixels PX. The control signal line CSL may provide controlsignals to the scan driving circuit. The signal pads DP-PD may beconnected to corresponding signal lines of the plurality of signal linesSGL.

A circuit board may be electrically connected to the display panel DP.The circuit board may be a rigid or flexible circuit board. A drivingchip may be mounted on the circuit board.

The driving chip may be mounted on the display panel DP. If the drivingchip is mounted on the display panel DP, the design or arrangement ofthe signal lines SGL may be changed. The driving chip may be connectedto the data lines DL, and signal lines may connect the driving chip tothe signal pads DP-PD.

FIG. 3A is an equivalent circuit diagram illustrating the pixel PXaccording to an exemplary embodiment of the inventive concept. FIGS. 3Band 3C are cross-sectional views illustrating a portion of the pixel PXaccording to an exemplary embodiment of the inventive concept. FIGS. 4Aand 4B are cross-sectional views illustrating a bending region BA of thedisplay panel DP according to an exemplary embodiment of the inventiveconcept.

FIG. 3A illustrates a scan line GL, a data line DL, a power line PL, anda pixel PX connected to the lines. In an exemplary embodiment of thepresent inventive concept, the pixel PX may be a light-emission typepixel, but the inventive concept is not limited thereto. For example,the pixel PX may include an organic light emitting diode or aquantum-dot light-emitting diode, which is used as a luminescent device.A luminescent layer of the organic light emitting diode may include anorganic luminescent material. A luminescent layer of the quantum-dotlight-emitting diode may include quantum dots and/or quantum rods. Forthe sake of simplicity, the description that follows will refer to anexample in which an organic light emitting pixel is used as the pixelPX, how it is to be understood that the present inventive concept may beimplemented with other types of pixels.

The pixel PX may include an organic light emitting diode OLED and apixel driving circuit for driving the organic light emitting diode OLED.The organic light emitting diode OLED may be a top-emission type diodeor a bottom-emission type diode. In an exemplary embodiment of thepresent inventive concept, the pixel driving circuit may include a firstthin-film transistor T1 (or a driving transistor), a second thin-filmtransistor T2 (or a switching transistor), and a capacitor Cst. A firstpower voltage ELVDD may be provided to the first thin-film transistorT1, and a second power voltage ELVSS may be provided to the organiclight emitting diode OLED. The second power voltage ELVSS may be lowerthan the first power voltage ELVDD.

The first thin-film transistor T1 may be connected to the organic lightemitting diode OLED. The first thin-film transistor T1 may control adriving current flowing through the organic light emitting diode OLED,depending on an amount of electric charge stored in the capacitor Cst.The second thin-film transistor T2 may be configured to output a datasignal applied to the data line DL, in response to a scan signal appliedto the scan line GL. The capacitor Cst may be charged to have a voltagecorresponding to a data signal received from the second thin-filmtransistor T2.

The structure of the pixel PX is not limited to the example of FIG. 3Aand may be variously changed. Unlike that shown in FIG. 3A, the pixelcircuit controlling the organic light emitting diode OLED may beconfigured to include three or more (e.g., six or seven) thin-filmtransistors. The organic light emitting diode OLED may be coupledbetween the power line PL and the second thin-film transistor T2.

FIG. 3B illustrates a vertical section of a portion of the pixel PXincluding the first thin-film transistor T1, the second thin-filmtransistor T2, and the organic light emitting diode OLED. As shown inFIG. 3B, the display panel DP may include a base layer BL and a circuitdevice layer DP-CL, a display device layer DP-OLED, and a thinencapsulation layer, which are disposed on the base layer BL. Thedisplay panel DP may further include functional layers, such as ananti-reflection layer and a refractive index adjusting layer. Thecircuit device layer DP-CL may include at least a plurality ofinsulating layers and a circuit device. Hereinafter, the insulatinglayers may include organic layers and/or inorganic layers.

The circuit device may include signal lines, pixel driving circuits, andso forth. The circuit device layer may be formed by forming aninsulating layer, a semiconductor layer, and a conductive layer using acoating or depositing process and then patterning the insulating layer,the semiconductor layer, and the conductive layer using aphotolithography process. The display device layer DP-OLED may include aluminescent device. The display device layer DP-OLED may further includean organic layer, which may be formed of the same material as the pixeldefinition layer PDL.

The base layer BL may be formed of or may otherwise include a syntheticresin film. The synthetic resin layer may include a thermosetting resin.The synthetic resin layer may be a polyimide-based resin layer, however,the inventive concept is not limited to a specific material. Thesynthetic resin layer may include acryl resins, methacryl resins,polyisoprene resins, vinyl resins, epoxy resins, urethane resins,cellulose resins, siloxane resins, polyamide resins, and/or peryleneresins. In an exemplary embodiment of the present inventive concept, thebase layer BL may include a glass substrate, a metal substrate, and/oran organic/inorganic composite substrate.

The base layer BL may be sectioned in the same manner as the displaypanel DP described with reference to FIGS. 1A to 2 . For example, thebase layer BL may include a first region NBA and a second region BA bentfrom the first region NBA. For example, the second region BA may beextended from the first region NBA and may be bendable.

At least one inorganic layer may be formed on a top surface of the baselayer BL. The inorganic layer may include aluminum oxide, titaniumoxide, silicon oxide silicon oxynitride, zirconium oxide, and/or hafniumoxide. For example, a plurality of inorganic layers may have amulti-layered structure. The multi-layered inorganic layers mayconstitute a barrier layer BRL and/or a buffer layer BFL to be describedbelow. In an exemplary embodiment of the present inventive concept, thebarrier layer BRL and/or the buffer layer BFL may be optionally omitted.

The barrier layer BRL may be configured to prevent contaminants frominfiltrating into the display panel DP. The barrier layer BRL mayinclude a silicon oxide layer and a silicon nitride layer. In anexemplary embodiment of the present inventive concept, the barrier layerBRL may include a plurality of silicon oxide layers and a plurality ofsilicon nitride layers that are alternately stacked.

The buffer layer BEL may be disposed on the barrier layer BRL. Thebuffer layer BFL may be configured to increase an adhesion strengthbetween the base layer BL and conductive or semiconductor patterns. Thebuffer layer BFL may include a silicon oxide layer and a silicon nitridelayer. In an exemplary embodiment of the present inventive concept, thebuffer layer BFL may include a plurality of silicon oxide layers and aplurality of silicon nitride layers that are alternately stacked.

A first semiconductor pattern OSP1 may be disposed on the buffer layerBFL. The first semiconductor pattern OSP1 may include silicon. The firstsemiconductor pattern OSP1 may be formed of or may otherwise includepolycrystalline silicon. However, the inventive concept is not limitedthereto, and the first semiconductor pattern OSP1 may be formed of ormay otherwise include amorphous silicon. The first semiconductor patternOSP1 may include an input region (or a first portion), an output region(or a second portion), and a channel region (or a third portion) definedbetween the input and output regions. The channel region of the firstsemiconductor pattern OSP1 may be defined to correspond to a firstcontrol electrode GE1 to be described below. The input region and theoutput region may be doped with impurities, thereby providing the inputregion with a conductivity that is higher than that of the channelregion. For example, the input region and the output region may be dopedto have an n-type conductivity. In an exemplary embodiment of thepresent inventive concept, the first thin-film transistor T1 isillustrated to be of an n-type, but in an exemplary embodiment of thepresent inventive concept, the first thin-film transistor T1 may be ap-type transistor.

A first insulating layer 10 may be disposed on the buffer layer BFL. Thefirst insulating layer 10 may commonly overlap a plurality of the pixelsPX (e.g., see FIG. 1A) and may cover the first semiconductor patternOSP1. The first insulating layer 10 may be an inorganic layer and/or anorganic layer and may have a single- or multi-layered structure. Thefirst insulating layer 10 may include aluminum oxide, titanium oxide,silicon oxide, silicon oxynitride, zirconium oxide, and/or hafniumoxide. In an exemplary embodiment of the present inventive concept, thefirst insulating layer 10 may be a silicon oxide layer having asingle-layered structure.

The first control electrode GE1 may be disposed on the first insulatinglayer 10. The first control electrode GE1 may at least overlap a channelregion of the first semiconductor pattern OSP1.

A second insulating layer 20 may be disposed on the first insulatinglayer 10 to cover the first control electrode GE1. The second insulatinglayer 20 may commonly overlap a plurality of the pixels PX (e.g., seeFIG. 1 ). The second insulating layer 20 may be an inorganic layerand/or an organic layer and may have a single-layered structure ormulti-layered structure. The second insulating layer 20 may includealuminum oxide, titanium oxide, silicon oxide, silicon oxynitride,zirconium oxide, and/or hafnium oxide. In an exemplary embodiment of thepresent inventive concept, the second insulating layer 20 may be asingle silicon oxide layer.

An upper electrode UE may be further disposed on the second insulatinglayer 20. The upper electrode UE may overlap the first control electrodeGE1.

A third insulating layer 30 may be disposed on the second insulatinglayer 20 and may cover the upper electrode UE. The third insulatinglayer 30 may be an inorganic layer and/or an organic layer and may havea single- or multi-layered structure. The third insulating layer 30 maybe formed of or may otherwise include aluminum oxide, titanium oxide,silicon oxide, silicon oxynitride, zirconium oxide, and/or hafniumoxide. In an exemplary embodiment of the present inventive concept, thethird insulating layer 30 may be a single silicon oxide layer.

A second semiconductor pattern OSP2 may be disposed on the thirdinsulating layer 30. The second semiconductor pattern OSP2 may includeoxide semiconductors. The second semiconductor pattern OSP2 may includea crystalline or amorphous oxide semiconductor. For example, the oxidesemiconductors may include metal oxides, whose metallic element is zinc(Zn), indium (In), gallium (Ga), tin (Sn), and/or titanium (Ti), or mayinclude mixtures of zinc (Zn), indium (In), gallium (Ga), tin (Sn),and/or titanium (Ti) and oxides thereof. As an example, the oxidesemiconductor may include indium-tin oxide (ITO), indium-gallium-zincoxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indiumoxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tinoxide (IZTO), zinc-tin oxide (ZTO), and/or the like.

The second semiconductor pattern OSP2 may include an input region (or afirst portion), an output region (or a second portion), and a channelregion (or a third portion) defined between the input region and theoutput region. The input region and the output region may containimpurities or dopants. The channel region of the second semiconductorpattern SP2 may be defined to correspond to a second control electrodeGE2 to be described below.

A reduced metallic element may be used for the impurities in the secondsemiconductor pattern SP2. The input region and the output region maycontain a metallic element reduced from the metal oxide of the channelregion. Accordingly, it may be possible to reduce a leakage current ofthe second thin-film transistor T2, and thus, the second thin-filmtransistor T2 may be used as a switching device with greater on/offcharacteristics.

An insulating pattern GIP may be disposed on the channel region of thesecond semiconductor pattern OSP2. The second control electrode GE2 maybe disposed on the insulating pattern GIP. The second control electrodeGE2 may overlap, at least, the insulating pattern GIP. An edge of theinsulating pattern GIP may be aligned along an edge of the secondcontrol electrode GE2. The second control electrode GE2 may have thesame shape as the insulating pattern GIP, when viewed in a plan view.The second control electrode GE2 may be a structure within theinsulating pattern GIP, when viewed in a plan view.

A fourth insulating layer 40 may be disposed on the third insulatinglayer 30 to cover the second semiconductor pattern OSP2 and the secondcontrol electrode GE2. The fourth insulating layer 40 may be aninorganic layer and/or an organic layer and may have a single- ormulti-layered structure. The fourth insulating layer 40 may includealuminum oxide, titanium oxide, silicon oxide, silicon oxynitride,zirconium oxide, and/or hafnium oxide. In an exemplary embodiment of thepresent inventive concept, the fourth insulating layer 40 may include asilicon oxide layer and a silicon nitride layer. In an exemplaryembodiment of the present inventive concept, the fourth insulating layer40 may include a plurality of silicon oxide layers and a plurality ofsilicon nitride layers, which are alternately stacked.

A first input electrode DE1, a first output electrode SE1, a secondinput electrode DE2, and a second output electrode SE2 may be disposedon the fourth insulating layer 40. The first input electrode DE1 and thefirst output electrode SE1 may be coupled to the first semiconductorpattern OSP1 through a first contact hole CH1 and a second contact holeCH2, which are formed to expose the input region and the output region,respectively, of the first semiconductor pattern OSP1. The first contacthole CH1 and the second contact hole CH2 may penetrate the firstinsulating layer 10 to the fourth insulating layer 40.

The second input electrode DE2 and the second output electrode SE2 maybe coupled to the second semiconductor pattern OSP2 through a thirdcontact hole CH3 and a fourth contact hole CH4, which are formed toexpose the input region and the output region, respectively, of thesecond semiconductor pattern OSP2. The third contact hole CH3 and fourthcontact hole CH4 may penetrate the fourth insulating layer 40.

A fifth insulating layer 50 may be disposed on the fourth insulatinglayer 40 to cover the first input electrode DE1, the first outputelectrode SE1, the second input electrode DE2, and the second outputelectrode SE2. The fifth insulating layer 50 may be an organic layer andmay have a single- or multi-layered structure.

A connection electrode CNE may be disposed on the fifth insulating layer50. The connection electrode CNE may be connected to the first outputelectrode SE1 through a fifth contact hole CH5 penetrating the fifthinsulating layer 50. A sixth insulating layer 60 or a passivation layermay be disposed on the fifth insulating layer 50 to cover the connectionelectrode CNE. The sixth insulating layer 60 may be an organic layer andmay have a single- or multi-layered structure.

In an exemplary embodiment of the present inventive concept, the fifthinsulating layer 50 and the sixth insulating layer 60 may be a polyimideresin layer having a single-layered structure. However, the inventiveconcept is not limited thereto, and in an exemplary embodiment of thepresent inventive concept, the fifth insulating layer 50 and the sixthinsulating layer 60 may include acryl resins, methacryl resins,polyisoprene resins, vinyl resins, epoxy resins, urethane resins,cellulose resins, siloxane resins, polyamide resins, and/or peryleneresins.

The organic light emitting diode OLED may be disposed on the sixthinsulating layer 60. An anode AE of the organic light emitting diodeOLED may be disposed on the sixth insulating layer 60. The anode AE maybe connected to the connection electrode CNE through a sixth contacthole CH6 penetrating the sixth insulating layer 60. A pixel definitionlayer PDL may be disposed on the sixth insulating layer 60.

The pixel definition layer PDL may have an opening OP that exposes atleast a portion of the anode AE. The opening OP of the pixel definitionlayer PDL may define a light-emitting region PXA of each pixel. Forexample, a plurality of the pixels PX (e.g., see FIG. 1A) may beregularly arranged on a flat surface of the display panel DP (e.g., seeFIG. 1A). Regions, in which the pixels PX are disposed, may be ‘pixelregions’, and each of the pixel regions may include the light-emittingregion PXA and a non-light-emitting region NPXA adjacent to thelight-emitting region PXA. The non-light-emitting region NPXA mayenclose the light-emitting region PXA.

The display region DP-DA of FIGS. 1A and 1B may include a plurality ofpixel regions. For example, the display region DP-DA may include aplurality of the light-emitting regions PXA and the non-light-emittingregion NPXA, which encloses the plurality of the light-emitting regionsPXA. The hole control layer HCL may be commonly disposed in thelight-emitting region PXA and the non-light-emitting region NPXA. Thecommon layer, such as the hole control layer HCL, may be commonlydisposed in a plurality of the pixels PX. The hole control layer HCL mayinclude a hole transport layer and a hole injection layer.

An organic light emitting layer EML may be disposed on the hole controllayer HCL. The organic light emitting layer EML may be locally disposedexclusively on a region corresponding to the opening OP. The organiclight emitting layer EML may be divided into a plurality of patternsthat are respectively formed in the pixels PX.

In an exemplary embodiment of the present inventive concept, the organiclight emitting layer EML is illustrated to have a patterned structure,but in an exemplary embodiment of the present inventive concept, theorganic light emitting layer EML may be commonly disposed in a pluralityof the pixels PX. Here, the organic light emitting layer EML may beconfigured to emit a white-color light. Furthermore, the organic lightemitting layer EML may have a multi-layered structure.

An electron control layer ECL may be disposed on the organic lightemitting layer EML. The electron control layer ECL may include anelectron transport layer and an electron injection layer. A cathode CEmay be disposed on the electron control layer ECL. The electron controllayer ECL and the cathode CE may be commonly disposed in a plurality ofthe pixels PX.

A thin encapsulation layer TFE may be disposed on the cathode CE. Thethin encapsulation layer TFE may commonly cover a plurality of thepixels PX. In an exemplary embodiment of the present inventive concept,the thin encapsulation layer TFE may directly cover the cathode CE. Inan exemplary embodiment of the present inventive concept, a cappinglayer may cover the cathode CE. In an exemplary embodiment of thepresent inventive concept, a stacking structure of the organic lightemitting diode OLED may have a shape obtained by reversing the structureillustrated in FIG. 3B.

The thin encapsulation layer TFE may include an inorganic layer and/oran organic layer. In an exemplary embodiment of the present inventiveconcept, the thin encapsulation layer TFE may include two inorganiclayers and an organic layer therebetween. In an exemplary embodiment ofthe present inventive concept, the thin encapsulation layer TFE mayinclude a plurality of inorganic layers and a plurality of organiclayers, which are alternately stacked (e.g. an inorganic layer over anorganic layer over an inorganic layer, etc.).

The inorganic encapsulation layer may protect the organic light emittingdiode OLED from moisture or oxygen, and the organic encapsulation layermay protect the organic light emitting diode OLED from contaminants(e.g., dust particles). The inorganic encapsulation layer may include asilicon nitride layer, a silicon oxynitride layer, a silicon oxidelayer, a titanium oxide layer, and/or an aluminum oxide layer, but theinventive concept is not limited thereto. The organic encapsulationlayer may include an acrylic organic layer, but the inventive concept isnot limited thereto.

In an exemplary embodiment of the present inventive concept, the firstthin-film transistor T1 may contain silicon (e.g. poly silicon), therebyhaving high electron mobility. The second thin-film transistor T2 maycontain an oxide semiconductor material, and this may make it possibleto reduce a leakage current. As a result, it may be possible to reduce adriving voltage of the pixel PX (e.g., see FIG. 3A) and to prevent thepixel PX from malfunctioning.

In an exemplary embodiment of the present inventive concept, a firstelectrode E1 and a second electrode E2 of the capacitor Cst may beformed by the same process as elements of the first thin-film transistorT1, as shown in FIG. 3C.

The first electrode E1 of the capacitor Cst may be disposed on the firstinsulating layer 10. The first electrode E1 may be formed by the sameprocess as the first control electrode GE1. The first electrode E1 maybe connected to the first control electrode GE1. The second insulatinglayer 20 may cover the first electrode E1. The second electrode E2 ofthe capacitor Cst may be disposed on the second insulating layer 20.

In an exemplary embodiment of the present inventive concept, the upperelectrode UE may be electrically connected to the second electrode E2.Furthermore, the upper electrode UE and the second electrode E2 may beformed through the same process, and in an exemplary embodiment of thepresent inventive concept, the upper electrode UE and the secondelectrode E2 may be connected to each other, thereby forming a singlebody. The third insulating layer may be disposed on the secondinsulating layer 20 to cover the second electrode E2 and the upperelectrode UE.

Each of FIGS. 4A and 4B illustrates a vertical section of the curvatureregion CA of FIG. 2 , taken parallel to the first direction DR1. FIG. 4Ais a vertical section of a portion that overlaps the signal line DL, andFIG. 4B is a vertical section of a portion, in which the signal line DLis not disposed. In FIG. 4A, the data line DL is illustrated as thesignal line SGL.

As shown in the vertical sections of FIGS. 4A and 4B, the second regionBA may have a stacking structure that is similar to that of the firstregion NBA (e.g., of the display region DP-DA). The barrier layer BRL,the buffer layer BFL, and the first to sixth insulating layers 10 to 60may be sequentially disposed on the top surface of the base layer BL.

A groove GV-1 (hereinafter referred to as a “lower groove”) may bedefined in the barrier layer BRL and/or the buffer layer BFL to overlapthe second region BA. The lower groove GV-1 may be defined in thecurvature region CA. For example, the inorganic layers BRL and BFL,which are placed below the first semiconductor pattern OSP1 (e.g., seeFIGS. 3B and 3C), may overlap the display region DP-DA and may extend tothe second region BA. The lower groove GV-1 may be defined in theinorganic layers BRL and BFL. When measured in the first direction DR1,a width of the base layer BL exposed by the lower groove GV-1 may besmaller than a width of the curvature region CA.

A groove GV-2 (hereinafter referred to as an “upper groove”) may bedefined in the first to fourth insulating layers 10 to 40 and mayoverlap the second region BA. The upper groove GV-2 may be defined inthe curvature region CA. In an exemplary embodiment of the presentinventive concept, the first to fourth insulating layers 10 to 40 maypartially expose a top surface of the topmost layer of the inorganiclayers including the barrier layer BRL and the buffer layer BFL.

Side surfaces of the barrier layer BRL and the buffer layer BFL definingthe lower groove GV-1 may be inclined at an angle, when viewed in across-sectional view. Side surfaces of the first to fourth insulatinglayers 10 to 40 defining the upper groove GV-2 may be inclined at anangle, when viewed in a cross-sectional view.

In an exemplary embodiment of the present inventive concept, whenmeasured in the first direction DR1, a width of the upper groove GV-2 atthe level of the fourth insulating layer may be larger than a width ofthe curvature region CA.

The fifth insulating layer 50, which is an organic layer, may bedisposed in the lower groove GV-1 and the upper groove GV-2. The fifthinsulating layer 50 may be in contact with a top surface of the baselayer BL, an inclined surface of the lower groove GV-1, and an inclinedsurface of the upper groove GV-2. The fifth insulating layer 50 may bein contact with a portion of the top surface of the buffer layer BFLexposed through the first to sixth insulating layers 10 to 60. Byproviding the organic layer in the bending region, flexibility of thebending region may be increased.

At least a portion of the signal line DL may be disposed on the fifthinsulating layer 50. The sixth insulating layer 60 may cover and protectthe signal line DL. Another portion of the signal line DL (e.g., locatedon the display region DP-DA) may be disposed on a layer different fromthe fifth insulating layer 50. For example, the other portion of thesignal line DL may be disposed on the fourth insulating layer 40. Theportion and the other portion of the signal line DL may be connectedthrough contact holes penetrating the fifth insulating layer 50. Thesecontact holes may be disposed in the non-display region DP-NDA of thefirst region NBA.

In an exemplary embodiment of the present inventive concept, at leastone of the layers disposed on the display region DP-DA may be extendedonto a top surface of the sixth insulating layer 60.

FIGS. 5A to 5M are cross-sectional views illustrating a process offabricating the display panel DP, according to an exemplary embodimentof the inventive concept. Each of FIGS. 5A to 5M is provided tocomparatively illustrate two regions corresponding to those of FIGS. 3Band 4A. For concise description, an element previously described withreference to FIGS. 1 to 4B may be identified by the same referencenumber without repeating an overlapping description thereof.

As shown in FIG. 5A, at least one inorganic layer may be formed on thefirst region NBA and the second region BA of the base layer BL. In thefabricating process of the display panel, the base layer BL may beplaced on a working substrate. The working substrate may be removed,after the fabricating process of the display panel.

Inorganic layers may be formed by depositing, coating, or printing aninorganic material. A silicon oxide layer and a silicon nitride layermay be sequentially formed to form the barrier layer BRL. A siliconoxide layer and a silicon nitride layer may be sequentially formed onthe barrier layer BRL to form the buffer layer BFL.

As shown in FIG. 5A, a first preliminary semiconductor pattern OSP1-Pmay be formed on the inorganic layers. The first preliminarysemiconductor pattern OSP1-P may be formed by forming and pattering asemiconductor layer. The semiconductor layer may be crystallized beforeor after the patterning of the semiconductor layer. A doping process maybe performed on the first preliminary semiconductor pattern OSP1-P.

Thereafter, as shown in FIG. 5B, the first insulating layer 10 may beformed on the first region NBA and the second region BA of the inorganiclayer. The first insulating layer 10 may be formed by a depositing,coating, or printing process. Insulating layers to be disposed on thefirst insulating layer 10 may also be formed by a depositing, coating,or printing process.

The first control electrode GE1 may be formed on the first insulatinglayer 10. The formation of the first control electrode GE1 may includeforming a conductive layer on the first insulating layer 10 and thenpatterning the conductive layer. The first electrode E1 of the capacitorCst may be formed by the same process as the first control electrodeGE1.

Next, the first preliminary semiconductor pattern OSP1-P may be dopedusing the first control electrode GE1 as a mask. A region (hereinafterreferred to as a “channel region”) overlapping the first controlelectrode GE1 may remain undoped, and two regions (hereinafter referredto as an “input region” and an “output region”), which are located atboth sides of the channel region, may be doped. In an exemplaryembodiment of the present inventive concept, n-type dopants (e.g., groupV elements) may be used for the doping process. As a result, the firstsemiconductor pattern OSP1 may be formed.

Hereinafter, as shown in FIG. 5C, the second insulating layer 20 may beformed on the first region NBA and the second region BA of the firstinsulating layer 10 to cover the first control electrode GE1. The upperelectrode UE may be formed on the second insulating layer 20. The secondelectrode E2 of the capacitor Cst may be formed by the same process asthe upper electrode UE.

Thereafter, as shown in FIG. 5D, the third insulating layer 30 may beformed on the first region NBA and the second region BA of the secondinsulating layer 20 to cover the upper electrode UE. A secondpreliminary semiconductor pattern OSP2-P may be formed on the thirdinsulating layer 30. The second preliminary semiconductor pattern OSP2-Pmay be formed from a semiconductor layer through a photolithographyprocess.

Next, as shown in FIG. 5E, an intermediate insulating layer 35 may beformed on the first region NBA and the second region BA of the thirdinsulating layer 30 to cover the second preliminary semiconductorpattern OSP2-P. The second control electrode GE2 may be formed on theintermediate insulating layer 35. The second control electrode GE2 maybe formed from a conductive layer through a photolithography process.

Thereafter, as shown in FIG. 5F, the insulating pattern GIP may beformed from the intermediate insulating layer 35 of FIG. 5E. Theinsulating pattern GIP may be formed by pattering the intermediateinsulating layer 35 using an etching gas. In an exemplary embodiment ofthe present inventive concept, the second control electrode GE2 may beused as an etching mask for selectively etching the intermediateinsulating layer 35. Thus, edges of the insulating pattern GIP and thesecond control electrode GE2 may be aligned to each other.

Next, as shown in FIG. 5G, the fourth insulating layer 40 may be formedon the first region NBA and the second region BA of the third insulatinglayer 30 to cover the second control electrode GE2. A silicon oxidelayer and a silicon nitride layer may be sequentially formed.

In the process of forming the fourth insulating layer 40, regions of thesecond preliminary semiconductor pattern OSP2-P (e.g., see FIG. 5F) thatare exposed to the outside may be reduced. For example, two oppositeregions of the second preliminary semiconductor pattern OSP2-P may bereduced, and the reduced regions may be an input region and an outputregion. The input region and the output region may contain a metallicmaterial that is reduced from a metal oxide semiconductor material. Aregion, which overlaps the insulating pattern GIP and is placed betweenthe input region and the output region, may be a channel region. As aresult, the first semiconductor pattern OSP1 may be formed. Anadditional reduction process may be further performed on the exposedregions of the second preliminary semiconductor pattern OSP2-P (e.g.,see FIG. 5F).

Thereafter, a portion of the insulating layers 10 to 40 may be removed(hereinafter, a first etching step). The contact holes CH1 and CH2 mayexpose the input region and the output region of the first semiconductorpattern OSP1. During the formation of the contact holes CH1 and CH2, thefirst to fourth insulating layers 10 to 40 may be partially removed onthe second region BA, thereby forming the upper groove GV-2.

Thereafter, as shown in FIG. 5H, other portion of the insulating layers10 to 40 and a portion of the inorganic layers may be removed(hereinafter, a second etching step). The contact holes CH3 and CH4 mayexpose the input region and the output region of the secondsemiconductor pattern OSP2. During the formation of the contact holesCH3 and CH4, the barrier layer BRL and the buffer layer BFL may bepartially removed on the second region BA, thereby forming the lowergroove GV-1.

As shown in FIGS. 5G and 5H, the contact holes CH1, CH2, CH3, and CH4and the grooves GV-1 and GV-2 may be formed by using a mask and anetching gas or by using a laser. Since each of the grooves GV-1 and GV-2is formed using the same process as corresponding ones of the contactholes CH1, CH2, CH3, and CH4, it may be possible to reduce the totalnumber of masks for the fabrication process. Furthermore, since theupper groove GV-2 and the lower groove GV-1 are formed by differentprocesses, the upper groove GV-2 and the lower groove GV-1 may have aheight difference, and thus, a portion of the top surface of the bufferlayer BFL may be exposed through the insulating layers 10 to 40.

Next, as shown in FIG. 5I, the electrodes DE1, SE1, SE2, and DE2 may beformed on the fourth insulating layer 40. The electrodes DE1, SE1, SE2,and DE2 may be formed through a deposition process.

Thereafter, as shown in FIG. 5J, the fifth insulating layer 50 may beformed on the fourth insulating layer 40 to cover the electrodes DE1,SE1, SE2, and DE2. The fifth insulating layer 50 may overlap the firstregion NBA and the second region BA. The fifth insulating layer 50 maybe disposed in the lower groove GV-1 and the upper groove GV-2. Thefifth contact hole CH5 exposing the first output electrode SE1 may beformed in the fifth insulating layer 50.

Next, as shown in FIG. 5K, the connection electrode CNE may be formed onthe fifth insulating layer 50. A portion of the signal line DL overlapsthe second region BA may be formed by the same process as the connectionelectrode CNE.

Thereafter, as shown in FIG. 5L, the sixth insulating layer 60 may beformed on the fifth insulating layer 50 to cover not only the connectionelectrode CNE but also the portion of the signal line DL overlaps thesecond region BA. The sixth contact hole CH6 may be formed in the sixthinsulating layer 60 to expose a top surface of the connection electrodeCNE.

Next, as shown in FIG. 5M, the organic light emitting diode OLED may beformed on the sixth insulating layer 60. The anode AE may be formed onthe sixth insulating layer 60 and may be connected to the connectionelectrode CNE through the sixth contact hole CH6. The pixel definitionlayer PDL may be formed on the sixth insulating layer 60 to expose acenter portion of the anode AE. A preliminary pixel definition layer maybe formed on the sixth insulating layer 60. The opening OP may be formedin the preliminary pixel definition layer.

Next, the hole control layer HCL, the light emitting layer EML, theelectron control layer ECL, and the cathode CE may be sequentiallyformed on the first region NBA of the pixel definition layer PDL. Thehole control layer HCL, the light emitting layer EML, the electroncontrol layer ECL, and the cathode CE may overlap at least the displayregion DP-DA (e.g., see FIG. 2 ), when viewed in a plan view.

The thin encapsulation layer TFE may be formed on the cathode CE. Anorganic encapsulation layer and/or an inorganic encapsulation layer maybe formed by a depositing or inkjet printing process. The thinencapsulation layer TFE may be formed exclusively on the first regionNBA and not on the second region BA.

FIGS. 6 to 9 are cross-sectional views illustrating a portion of thedisplay panel DP according to an exemplary embodiment of the inventiveconcept. Each of FIGS. 6 to 9 illustrate a section corresponding to FIG.5M. For concise description, an element previously described withreference to FIGS. 1 to 5M may be identified by the same referencenumber without repeating an overlapping description thereof.

As shown in FIG. 6 , the connection electrode CNE and the sixthinsulating layer 60 may be omitted. The anode AE may be directlydisposed on the fifth insulating layer 50 and may be connected to thefirst output electrode SE1 through the fifth contact hole CH5. A portionof the signal line DL overlapping the second region BA may be directlydisposed on the fifth insulating layer 50.

The portion of the signal line DL overlapping the second region BA maybe formed by the same process as the anode AE. The portion of the signalline DL overlapping the second region BA and the anode AE may includethe same material and may have the same layer structure.

As shown in FIG. 7 , the intermediate insulating layer 35 may be furtherdisposed between the third insulating layer 30 and the fourth insulatinglayer 40. The intermediate insulating layer 35 may overlap the firstregion NBA and the second region BA.

Openings 35-OP corresponding to the input region and the output regionof the second semiconductor pattern OSP2 may be formed in theintermediate insulating layer 35. As shown in FIG. 5E, the openings35-OP may be formed after the formation of the intermediate insulatinglayer 35 and the second control electrode GE2. Thereafter, the fourthinsulating layer 40 may be formed. The upper groove GV-2 may be formedby removing not only the first to fourth insulating layers 10 to 40 butalso by removing the intermediate insulating layer 35.

In an exemplary embodiment of the present inventive concept, the thirdcontact hole CH3 and the fourth contact hole CH4 may penetrate theintermediate insulating layer 35 and the fourth insulating layer 40, andin this case, the additional process for forming the openings 35-OP inthe intermediate insulating layer 35 may be omitted.

Referring to FIG. 8 , the upper electrode UE and the second controlelectrode GE2 may include the same material and have the same stackingstructure. The upper electrode UE and the second control electrode GE2may be formed from the same conductive layer.

The upper electrode UE may be formed in the step of FIG. 5E, rather thanin the step of FIG. 5C. However, after the formation of the intermediateinsulating layer 35 shown in FIG. 5E and before formation of aconductive layer, the intermediate insulating layer 35 may be patternedto form the insulating pattern GIP. A conductive layer may be formed onthe third insulating layer 30 to cover the insulating pattern GIP, andthen, the conductive layer may be patterned to form the upper electrodeUE and the second control electrode GE2. The second electrode E2 mayalso be formed by the same process as the upper electrode UE.

As shown in FIG. 9 , the upper electrode UE and the second controlelectrode GE2 may be disposed on the same layer, may include the samematerial, and may have the same stacking structure. The upper electrodeUE and the second control electrode GE2 may be formed from the sameconductive layer.

The upper electrode UE may be formed in the step of FIG. 5E, rather thanin the step of FIG. 5C, and in this case, the display panel DP may havethe structure of FIG. 9 . For example, a process of forming the secondcontrol electrode GE2 may include forming a conductive layer on theintermediate insulating layer 35 and then patterning the conductivelayer, and here, the upper electrode UE may be formed using the processfor forming the second control electrode GE2. Thereafter, theintermediate insulating layer 35 may be etched using the second controlelectrode GE2 and the upper electrode UE as an etch mask.

A first insulating pattern GIP1 and a second insulating pattern GIP2,which overlap the second control electrode GE2 and the upper electrodeUE, respectively, may be formed from the intermediate insulating layer35 of FIG. 5E. An edge of the second insulating pattern GIP2 may bealigned along an edge of the upper electrode UE. The upper electrode UEmay have the same shape as that of the second insulating pattern GIP2,when viewed in a plan view.

FIGS. 10A to 10G are cross-sectional views illustrating a portion of thedisplay panel DP according to an exemplary embodiment of the inventiveconcept. Each of FIGS. 10A to 10G illustrates a section corresponding toFIG. 5M. For concise description, an element previously described withreference to FIGS. 1 to 9 may be identified by the same reference numberwithout repeating an overlapping description thereof.

As shown in FIGS. 10A to 10G, the display panel DP may further include alight blocking pattern LSP, which is disposed between the buffer layerBFL and the first insulating layer 10 and overlaps the secondsemiconductor pattern OSP2.

The light blocking pattern LSP may be formed of or may otherwise includea material having high optical absorptivity or high optical reflectance.The light blocking pattern LSP N) may be disposed below the secondsemiconductor pattern OSP2 to prevent external light from being incidentinto the second semiconductor pattern SP2. In this case, it may bepossible to prevent a voltage-current property of the secondsemiconductor pattern SP2 from being affected by an external light andthereby to prevent a leakage current from occurring in the secondsemiconductor pattern SP2.

As shown in FIG. 10A, the light blocking pattern LSP may include thesame material as that of the first semiconductor pattern OSP1. Forexample, the light blocking pattern LSP may include a doped crystallinesemiconductor pattern.

The light blocking pattern LSP may be formed by the same process as thefirst preliminary semiconductor pattern OSP1-P of FIG. 5A. Thereafter,the light blocking pattern LSP may be doped during the processillustrated in FIG. 5B.

As shown in FIG. 10B, the light blocking pattern LSP may include thesame material as the first control electrode GEL. The light blockingpattern LSP may be formed by the same process as the first controlelectrode GE1 shown in FIG. 5B. As shown in FIG. 10C, the light blockingpattern LSP may include the same material as the upper electrode UE. Thelight blocking pattern LSP may be formed by the same process as theupper electrode UE shown in FIG. 5C. The light blocking pattern LSP mayhave a single- or multi-layered structure. The light blocking patternLSP may have the same stacking structure as the first control electrodeGE1 or the upper electrode UE. Similar to the first control electrodeGE1, the light blocking pattern LSP may include a molybdenum layer.

In FIGS. 10A to 10C, the light blocking pattern LSP may be a floatingelectrode. The light blocking pattern LSP to be described below may beconfigured to receive a specific voltage or a specific signal.

As shown in FIGS. 10D to 10F, the light blocking pattern LSP may beconnected to a signal line SGL-P. The signal line SGL-P and the firstinput electrode DE1 may be formed on the same layer through the sameprocess, as illustrated in FIGS. 10D to 10F. The light blocking patternLSP and the signal line SGL-P may be connected to each other through aseventh contact hole CH7, which is formed to penetrate the first tofourth insulating layers 10 to 40.

As shown in FIG. 10E, the light blocking pattern LSP may be disposed onthe first insulating layer 10, and the light blocking pattern LSP andthe signal line SGL-P may be connected to each other through the seventhcontact hole CH7 penetrating the second to fourth insulating layers 20to 40. As shown in FIG. 10F, the light blocking pattern LSP may bedisposed on the second insulating layer 20, and the light blockingpattern LSP and the signal line SGL-P may be connected to each otherthrough the seventh contact hole CH7 penetrating the third and fourthinsulating layers 30 and 40.

The light blocking pattern LSP of FIG. 10E may have a small heightdifference from the third insulating layer 30, compared with the lightblocking pattern LSP of FIG. 10F. Furthermore, the third insulatinglayer 30 in contact with the second semiconductor pattern OSP2 mayprevent diffusion of impurities in the light blocking pattern LSP.Since, as shown in FIG. 10E, the second insulating layer 20 covers thelight blocking pattern LSP, it may be possible to deposit the thirdinsulating layer 30 without the light blocking pattern LSP contaminatingthe third insulating layer 30. The second insulating layer 20 may be asilicon nitride layer, and the third insulating layer 30 may be asilicon oxide layer.

Due to a process error, the second thin-film transistor T2 may have athreshold voltage that is different from a desired value. In anexemplary embodiment of the present inventive concept, a specific biasvoltage may be applied to the light blocking pattern LSP of FIGS. 10D to10F, and in this case, the second thin-film transistor T2 may becontrolled to have a desired threshold voltage. For example, in the casewhere the threshold voltage of the second thin-film transistor T2 issmaller than a desired value, the second thin-film transistor T2 maysuffer from an increased leakage current. In this case, by applying abias voltage to the light blocking pattern LSP of the second thin-filmtransistor T2, it may be possible to compensate the negative shiftphenomenon in threshold voltage of the second thin-film transistor T2.

As shown in FIG. 10G, the signal line SGL-P may be connected to thesecond control electrode GE2 through an eighth contact hole CH8. Thesignal line SGL-P may be configured to electrically connect the lightblocking pattern LSP, which is formed of a crystalline semiconductormaterial, to the second control electrode GE2. Accordingly, the lightblocking pattern LSP may be used as a control electrode of controllingflow of electric charge in the channel region of the secondsemiconductor pattern SP2. For example, the second thin-film transistorT2 may include two control electrodes, which are electrically connectedto each other. The two control electrodes may be configured to receivethe same signal. In an exemplary embodiment of the present inventiveconcept, the light blocking pattern LSP of FIG. 10G may be disposed onother layer, as shown in FIGS. 10E and 10F.

FIGS. 11A to 11L are cross-sectional views illustrating a portion of adisplay panel according to an exemplary embodiment of the inventiveconcept. In the display panels DP of FIGS. 11A to 11L, the shape of thesignal line DL may be partly different from that in the display panel DPof FIG. 5M.

As shown in FIGS. 11A to 11D, the signal line DL may include a firstportion DL1-P1, a second portion DL1-P2, and a third portion DL1-P3. Thefirst portion DL1-P1 may be connected to the pixel PX (e.g., see FIG. 2), and the third portion DL1-P3 may be connected to a corresponding oneof the signal pads DP-PD (e.g., see FIG. 2 ) or another driving chip.The second portion DL1-P2 may connect the first portion DL1-P1 to thethird portion DL1-P3 through the seventh contact hole CH7 and the eighthcontact hole CH8. The second portion DL1-P2 may overlap the curvatureregion CA.

As shown in FIG. 11A, the first portion DL1-P1 and the third portionDL1-P3 may be formed by the same process as the input and outputelectrodes DE1, SE1, SE2, and DE2 of the transistors T1 and T2 and maybe formed on the same layer as the input and output electrodes DE1, SE1,SE2, and DE2 of the transistors T1 and T2. Each of the seventh contacthole CH7 and the eighth contact hole CH8 may penetrate the fifthinsulating layer 50. Each of the seventh contact hole CH7 and the eighthcontact hole CH8 may be formed by the same process as the fifth contacthole CH5.

As shown in FIG. 11B, the first portion DL1-P1 and the third portionDL1-P3 may be formed by the same process as the second control electrodeGE2 and may be formed on the same layer as the second control electrodeGE2. Each of the seventh contact hole CH7 and the eighth contact holeCH8 may penetrate the fourth insulating layer 40 and the fifthinsulating layer 50. Each of the seventh contact hole CH7 and the eighthcontact hole CH8 may be formed using the process for forming the fourthcontact hole CH4 and the fifth contact hole CH5. In an exemplaryembodiment of the present inventive concept, the seventh contact holeCH7 and the eighth contact hole CH8 may be formed by an additionalprocess.

As shown in FIG. 11C, the first portion DL1-P1 and the third portionDL1-P3 may be formed by the same process as the upper electrode UE andmay be formed on the same layer as the upper electrode UE. Each of theseventh contact hole CH7 and the eighth contact hole CH8 may penetratethe third insulating layer 30, the fourth insulating layer 40, and thefifth insulating layer 50.

As shown in FIG. 11D, the first portion DL1-P1 and the third portionDL1-P3 may be formed by the same process as the first control electrodeGE1 and may be formed on the same layer as the first control electrodeGE1. Each of the seventh contact hole CH7 and the eighth contact holeCH8 may penetrate the second insulating layer 20, the third insulatinglayer 30, the fourth insulating layer 40, and the fifth insulating layer50.

In the approach discussed above with respect to FIGS. 11C and 11D, eachof the seventh contact hole CH7 and the eighth contact hole CH8 may beformed using the process for forming the second contact hole CH2 and thefifth contact hole CH5. In an exemplary embodiment of the presentinventive concept, the seventh contact hole CH7 and the eighth contacthole CH8 may be formed by an additional process.

Each of the display panels DP of FIGS. 11E to 11J may further include afirst connection electrode CNE-D1 and a second connection electrodeCNE-D2, compared with the display panels DP of FIGS. 11A to 11D.

As shown in FIG. 11E, the first portion DL1-P1 and the third portionDL1-P3 may be formed by the same process as the second control electrodeGE2 and may be formed on the same layer as the second control electrodeGE2. The first connection electrode CNE-D1 and the second connectionelectrode CNE-D2 may be formed by the same process as the input andoutput electrodes DE1, SE1, SE2, and DE2 of the transistors T1 and T2and may be formed on the same layer as the input and output electrodesDE1, SE1, SE2, and DE2 of the transistors T1 and T2.

The seventh contact hole CH7 may connect the first connection electrodeCNE-D1 to the first portion DL1-P1, and the eighth contact hole CH8 mayconnect the second connection electrode CNE-D2 to the third portionDL1-P3. Each of the seventh contact hole CH7 and the eighth contact holeCH8 may be formed by the same process as the fourth contact hole CH4. Aninth contact hole CH9 may connect the second portion DL1-P2 to thefirst connection electrode CNE-D1, and a tenth contact hole CH10 mayconnect the second portion DL1-P2 to the second connection electrodeCNE-D2. Each of the ninth contact hole CH9 and the tenth contact holeCH10 may be formed by the same process as the fifth contact hole CH5.

As shown in FIGS. 11F and 11G, sectional positions of the first portionDL1-P1 and the third portion DL1-P3 may be changed. As shown in FIGS.11H to 11J, the first portion DL1-P1 and the third portion DL1-P3 may bedisposed on different layers.

As shown in FIG. 11H, the first portion DL1-P1 may be disposed on thethird insulating layer 30, and the third portion DL1-P3 may be disposedon the second insulating layer 20. As shown in FIG. 11I, the firstportion DL1-P1 may be disposed on the third insulating layer 30, and thethird portion DL1-P3 may be disposed on the first insulating layer 10.As shown in FIG. 11J, the first portion DL1-P1 may be disposed on thesecond insulating layer 20, and the third portion DL1-P3 may be disposedon the first insulating layer 10. In an exemplary embodiment of thepresent inventive concept, the sectional positions of the first portionDL1-P1 and the third portion DL1-P3 may be interchanged with each other.

Each of the display panels DP of FIGS. 11K and 11L may further includethe connection electrode CNE-D, compared with the display panels DP ofFIGS. 11A to 11D. In the display panels DP of FIGS. 11K and 11L, thenumber of the connection electrode CNE-D may be reduced, compared withthe display panels DP of FIGS. 11E and 11H.

As shown in FIG. 11K, the first portion DL1-P1 may be formed by the sameprocess as the upper electrode UE and may be formed on the same layer asthe upper electrode UE, and the connection electrode CNE-D may be formedby the same process as the second control electrode GE2 and may beformed on the same layer as the second control electrode GE2. In anexemplary embodiment of the present inventive concept, an additionalprocess may be performed to form the seventh contact hole CH7penetrating the third insulating layer 30. Each of the eighth contacthole CH8 and the ninth contact hole CH9 may be formed using the processfor forming the fifth contact hole CH5.

As shown in FIG. 11K, the first portion DL1-P1 may be formed by the sameprocess as the first control electrode GE1 and may be formed on the samelayer as the first control electrode GE1, and the connection electrodeCNE-D may be formed by the same process as the second control electrodeGE2 and may be formed on the same layer as the second control electrodeGE2. In an exemplary embodiment of the present inventive concept, anadditional process may be performed to form the seventh contact holeCH47 penetrating the second insulating layer 20 and the third insulatinglayer 30. Each of the eighth contact hole CH8 and the ninth contact holeCH9 may be formed using the process for forming the fifth contact holeCH5.

In an exemplary embodiment of the present inventive concept, thesectional position of the connection electrode CNE-D may be changed fromthat shown in FIGS. 11K and 11L. The connection electrode CNE-D mayconnect the second portion DL1-P2 to the third portion DL1-P3.

According to an exemplary embodiment of the inventive concept, it may bepossible to reduce a leakage current of a thin-film transistor, which isdirectly connected to a signal line. It may be possible to maintain avoltage-current property of a thin-film transistor controlling a drivingcurrent of a luminescent device.

Since an organic layer is disposed on a bending region of a displaypanel, flexibility of the bending region of the display panel may beincreased.

A contact hole exposing a portion of a semiconductor pattern disposed ona display region may be formed concurrently using a process of etchingan insulating layer and an inorganic layer on the bending region, andthus, it may be possible to reduce the total number of masks for afabrication process.

While example embodiments of the inventive concept have beenparticularly shown and described, it will be understood by one ofordinary skill in the art that variations in form and detail may be madetherein without departing from the spirit and scope of the presentinventive concept.

What is claimed is:
 1. A display panel, comprising: a base layerincluding a first region and a second region that is bent with respectto the first region; at least one inorganic layer overlapping both thefirst region and the second region and disposed on the base layer; afirst thin-film transistor disposed on the at least one inorganic layerand including a silicon semiconductor pattern overlapping the firstregion; a second thin-film transistor disposed on the at least oneinorganic layer and including an oxide semiconductor pattern overlappingthe first region, wherein the oxide semiconductor pattern is disposed ona layer different from the silicon semiconductor pattern; a plurality ofinsulating layers overlapping both the first region and the secondregion; a signal line electrically connected to the second thin-filmtransistor; an organic layer overlapping both the first region; and aluminescent element disposed on the organic layer and overlapping thefirst region, and wherein an opening is defined in the at least oneinorganic layer and the plurality of insulation layers and the openingis positioned in the second region.